Transistors and similar semiconductor components have been scaled to increasingly smaller dimensions. As a result of this scaling, leakage currents have become a significant source of power consumption in devices. The power consumption resulting from leakage currents is of particular concern in devices having finite power available, such as battery-powered portable devices.
When transistors are in an off state (i.e., when the gate-to-source voltage Vgs is less than the threshold voltage Vth of the transistor), the current flow between the drain and the source of a transistor resulting from the diffusion of minority carriers in the well of the transistor is a substantial source of leakage current commonly referred to as the subthreshold leakage. To reduce the subthreshold leakage, the well of the transistor may be biased by a well bias voltage Vwb provided by a voltage source. However, it will be appreciated that the voltage source consumes power while providing the well bias voltage Vwb. Thus, if the voltage source is operated to provide a well bias voltage so that the voltage source itself operates inefficiently, the reduction in the subthreshold leakage by providing the well bias voltage Vwb may be offset by the excessive power consumption by the voltage source providing the well bias voltage Vwb.
Conventional approaches attempt to solve this discrepancy by maintaining the well bias voltage at a particular voltage value through a voltage monitoring process. However, these techniques fail to account for process and temperature variations which may cause excess power consumption at the preselected well bias voltage. Accordingly, a technique for biasing semiconductor components that improves power consumption would be advantageous.